//-----------------------------------------------------
// Design Name : bufferlt
// File Name : bufferlt.v
// Function : Latch and Tristate buffer. Parameterized for size
//-----------------------------------------------------
module bufferlt (
    Q,		// Output
    D,		// Input data
    CAPTURE,	// Update the internal latch
    READn	// Drive the output ports
  ); // End of port list

  //------------- PORT DECLARATIONS
  output [3:0] Q;
  input [3:0] D;
  input CAPTURE;
  input READn;

  //------------- DATA TYPES
  // Output port can be a storage element (reg) or a wire
  reg [3:0] Q;
  // Input ports are always wire, explicitly or by default.
  wire [3:0] D;
  wire CAPTURE;
  wire READn;

  // Internal Nodes
  reg [3:0] QINT;

  //------------ FUNCTIONAL CODE
  always @(posedge CAPTURE)
    begin
      QINT = D;
    end // always CAPTURE

  always @(READn or QINT)
    begin
      if( READn == 1'b0 ) begin
	Q = QINT;
      end else begin
	Q = 4'bz;
      end // if READn
    end // always READn
endmodule // bufferlt