module bufferlt_tb();
  // ------------- DECLARATIONS
  // Signals we will be controlling here are usually declared as reg.
  reg [3:0] D;	     // Data into the DUT
  reg CAPTURE;	     // Trigger the DUT to latch the data
  reg READn;	     // Active the output buffers of the DUT
  // Outputs from external modules must be declared as wire.
  wire [3:0] Q;

  // ------------- DUT
  bufferlt buf1 (
    .Q(Q),
    .D(D),
    .CAPTURE(CAPTURE),
    .READn(READn)
  );

  // ------------- FUNCTIONAL CODE
  // Initialize all variables
  initial begin
    $display ("time\t READn CAPTURE     D     Q");
    $monitor ("%g\t   %b     %b         %h     %h",
  	  $time, READn, CAPTURE, D, Q);
    READn = 1'b1;	// Don't look before loading data
    CAPTURE = 1'b0;	// Inactive
    D = 4'b0000;	// Nothing special on the inputs
    #5;
    CAPTURE = 1'b1;	// Load zeros
    #5;
    CAPTURE = 1'b0;
    READn = 1'b0;
    D = 4'b1111;
    #5;
    READn = 1'b1;
    #5;
    CAPTURE = 1'b1;
    #5;
    READn = 1'b0;
    #5;
    D = 4'b0101;
    #5;
    CAPTURE = 0;
    #5;
    READn = 1'b1;
    #5;
    CAPTURE = 1;
    #5;
    READn = 1'b0;
    D = 4'b1010;
    #5;
    CAPTURE = 0;
    #5;
    CAPTURE = 1;
    #5 $finish;	// Terminate simulation
  end // initial

endmodule // bufferlt_tb()