//-----------------------------------------------------
// Design Name : count_updn_en
// File Name : count_updn_en.v
// Function : Up-down counter with enable and reset.
// Reference:
//   http://www.asic-world.com/verilog/first1.html
//   Derived from that source, but with lots of edits
//-----------------------------------------------------
module count_updn_en (
    Q, Qn,	// counter output
    RSTn,	// active low synchronous reset
    UPDn,	// high=count up; low=count down
    ENBn,	// Active low enable signal for counter
    CLK		// Clock input of the design
  ); // End of port list

  //------------- PORT DECLARATIONS
  output [3:0] Q, Qn ;
  input CLK ;
  input RSTn ;
  input UPDn ;
  input ENBn ;
  //------------- DATA TYPES
  // Output port can be a storage element (reg) or a wire
   reg [3:0] Q;
   wire [3:0] Qn;
  // Input ports are always wire, explicitly or by default.

  //------------ FUNCTIONAL CODE
  // Since this counter is a positive edge trigged one,
  // We trigger the below block with respect to positive
  // edge of the clock.
  always @ (posedge CLK)
    begin : COUNTER // Block Name
      // At every rising edge of clock we check if reset is active
      // If active, we load the counter output with 4'b0000
      if (RSTn == 1'b0) begin
         Q = 0;
      end // if
      // If enable is active, then we increment the counter
      else
        if (ENBn == 1'b0) begin
	   if (UPDn == 1'b1) begin
	      Q = Q + 1;
           end else begin
	      Q = Q - 1;
           end // if
        end // if
    end // COUNTER

   assign Qn = ~Q;

endmodule // count_updn_en()