// Reference:
//   http://www.asic-world.com/verilog/first1.html
//   Derived from that source, but with edits to improve style

//`timescale 1 ns / 100 ps

module count_updn_en_tb();
  // ------------- DECLARATIONS
  // Signals we will be controlling here will be declared as reg.
  reg CLK, RSTn, UPDn, ENBn;
  // Outputs from external modules are always declared as wire.
  wire [3:0] Q, Qn;


  // ------------- DUT
  count_updn_en counter1 (
    .CLK(CLK),
    .RSTn(RSTn),
    .UPDn(UPDn),
    .ENBn(ENBn),
    .Q(Q),
    .Qn(Qn)
  );

  // ------------- FUNCTIONAL CODE
  // Initialize all variables
  initial begin
    $display ("time\t CLK RSTn UPDn ENBn Q  Qn");
    $monitor ("%g\t  %b   %b    %b    %b   %h  %h",
  	  $time, CLK, RSTn, UPDn, ENBn, Q, Qn);
    CLK = 1'b1;		// initial value of clock
    RSTn = 1'b0;	// initial value of reset
    UPDn = 1'bX;	// Shouldn't matter until enabled
    ENBn = 1'b1;	// initial value of enable
    #15 RSTn = 1'b1;	// Assert the reset
    #20 UPDn = 1'b1;	// De-assert the reset
    ENBn = 1'b0;  	// Assert enable
    #30 UPDn = 1'b0;	// Switch to count up
    #10 ENBn = 1'b1;
    #10 ENBn = 1'b0;
    UPDn = 1'b1;
    #30 RSTn = 1'b0;	// De-assert the reset
    #20 $finish;	// Terminate simulation
  end // initial

  // Clock generator
  always begin
    #5 CLK = ~CLK;	// Toggle clock every 5 ticks
  end // always

endmodule // count_updn_en_tb()