//-----------------------------------------------------
// This is my second Verilog Design
// Design Name : first_counter
// File Name : first_counter.v
// Function : This is a 4 bit up-counter with
//   Synchronous active high reset and
//   with active high enable signal
// Reference:
//   http://www.asic-world.com/verilog/first1.html
//   Derived from that source, but with edits to improve style
//-----------------------------------------------------
module first_counter (
    counter_out, // 4 bit vector output of the counter
    reset,	// active high, synchronous Reset input
    enable,	// Active high enable signal for counter
    clock	// Clock input of the design
  ); // End of port list

  //------------- PORT DECLARATIONS
  output [3:0] counter_out ;
  input clock ;
  input reset ;
  input enable ;
  //------------- DATA TYPES
  // Output port can be a storage element (reg) or a wire
  reg [3:0] counter_out ;
  // Input ports are always wire, explicitly or by default.

  //------------ FUNCTIONAL CODE
  // Since this counter is a positive edge trigged one,
  // We trigger the below block with respect to positive
  // edge of the clock.
  always @ (posedge clock)
    begin : COUNTER // Block Name
      // At every rising edge of clock we check if reset is active
      // If active, we load the counter output with 4'b0000
      if (reset == 1'b1)
      begin
        counter_out <= #1 4'b0000;
      end // if
      // If enable is active, then we increment the counter
      else
        if (enable == 1'b1)
        begin
          counter_out <= #1 counter_out + 1;
        end // if
    end // COUNTER

endmodule // first_counter()