// Reference:
//   http://www.asic-world.com/verilog/first1.html
//   Derived from that source, but with edits to improve style

//`timescale 1 ns / 100 ps

module first_counter_tb();
  // ------------- DECLARATIONS
  // Signals we will be controlling here will be declared as reg.
  reg clk, reset, enable;
  // Outputs from external modules are always declared as wire.
  wire [3:0] counter_out;


  // ------------- DUT
  first_counter counter1 (
    .clock(clk),
    .reset(reset),
    .enable(enable),
    .counter_out(counter_out)
  );

  // ------------- FUNCTIONAL CODE
  // Initialize all variables
  initial begin        
    $display ("time\t clk reset enable counter");	
    $monitor ("%g\t %b   %b     %b      %b", 
  	  $time, clk, reset, enable, counter_out);	
    clk = 1;		// initial value of clock
    reset = 0;		// initial value of reset
    enable = 0;		// initial value of enable
    #5 reset = 1;	// Assert the reset
    #10 reset = 0;	// De-assert the reset
    #10 enable = 1;	// Assert enable
    #100 enable = 0;	// De-assert enable
    #5 $finish;		// Terminate simulation
  end

  // Clock generator
  always begin
    #5 clk = ~clk;	// Toggle clock every 5 ticks
  end
    
endmodule