The following training material is available for students with limited knowlege of computers and electronics.

Verilog intro

Verilog

The modules below represent example code. They are presented roughly in order of difficulty. Students should write the modules themselves, which are presented below only for reference. Their modules should then be validated against the linked testbenches.

• Counter

  Up-down counter with enable and reset.
  • Makefile - How to compile and run
  • first_counter.v - Simple counter
  • first_counter_tb.v - The testbench
  • first_counter_tb.ref - The testbench output
  • count_updn_en.v - Simple counter
  • count_updn_en_tb.v - The testbench
  • count_updn_en_20080604.dia - The testbench output
  • count_updn_en_tb.ref - The testbench output

• Buffer

  Latch with Tristate output. Parameterized size.
  • Makefile - How to compile and run
  • bufferlt_tb.v - The testbench
  • bufferlt.v - Latch and tristate buffer
  • bufferlt_tb.ref - The testbench output

• Quadrature

  Quadrature decoder for driving the counter above